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| title | aliases | tags | sr-due | sr-interval | sr-ease | ||
|---|---|---|---|---|---|---|---|
| 02-combinatorial-logic |
|
2022-08-16 | 20 | 250 |
Circuit basics:
- current flows + to -
- input to a unit (e.g., LED) is the + end
Combinatorial Logic Circuit
[!Definition] Combinatorial Logic Circuit is a circuit whose digital outputs are dependent only on its digital inputs They can be described using logic expressions and therefore logic gates. We assume the outputs respond immediately^[1]
They can be defined:
-
Using a truth table
-
Using boolean equations (
Q\ =\ A+\ B) -
Using graphical symbols
-
3 Bit parity Generator
- Adds an extra bit to the input data so that the number of ones in the output is always odd
- Used for error checking
- truth table
- boolean equation
- circuit
Boolean Equations
Precedence
- NOT is unary, so it has the highest precedence
- AND is mulitply, so it comes next
- OR is like plusl, to it comes last
Creating boolean equations:
- for each row where output is 1
- write the equation as a function of the inputs (using AND)
- Write the final equation, putting OR between each clause
- example
De Morgan's Theorum
- !(A + B) = A! & !B
- !(A + B + C + ... + X) = !A & !B & !C & ... & !X
- truth table
- any boolean function can be represented as the sum of logical products
- All combinatorial circuits can be described using just one gate type (either nand or nor) [^2]
Transistors
- B: Base ⇒ A swtich connecting C to E
- open (C is disconnected from E) when supplied 0v
- closed (C is connected to E) by applying +5V
- C: Collector
- E: Emitter
Possible to create NAND gate using just transistors ∴ possible to create all logic gates using only transistors [^3]
Demultiplexor
- Mutli way swtich where the address determines which output recieves the input
- 2 bit address diagram and truth table
Logic Gates
- NOT
- AND
- OR
- NAND
- NOR
- XOR/EOR
[^1] : In real circuits propagation delay must be considered, hence the clock cycle on CPUs [^2] : The Apollo Guidance Computer used about 5600 NOR gates and no other gate types! [^3] : They dont actually do it this way (see lab)

