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71 lines
2.9 KiB
Markdown
71 lines
2.9 KiB
Markdown
---
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title: "21-memory-management"
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aliases:
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tags:
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- cosc204
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- lecture
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sr-due: 2022-11-22
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sr-interval: 14
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sr-ease: 250
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---
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# storage heirachy
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primary storage - cache and main memory
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secondaryy - hard drive
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as we move from secondary to primary:
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- access speed increases
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- access time decreases
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- cost increases
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- capacity decreases
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# process memory image and logical and physical addresses
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- a program is compiled and linked into a process image before loading into memory for execution
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- a process memory image consists of code section, data sections, lib sections, and stack sections
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- each process has its own logical memory space starting from 0 and ending at a maximum address
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- the logical address has to be translated into physical address before sending the memory request to the physical memory modules
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- the memory management unit (MMU) translated between the logical addresse and the physical addresses.
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- physical mode - progam refers directly to physical address
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- protected mode - dont allow program to use physical address directly - uses logical address
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- OS kernel creates a map from logical address to the physical address using a mapping table
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- CPUrefers to this table to map between physical and logical address
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# paging for memory translation
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Noncontiguous paging: a processes logica address pace is broken int fixed size units called pages, and main memory is broken into units of the same size, called frames.
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in a paged memory allocation scheme, the logical sddresses generated by the CPU are broken by special ardware itno two components:
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- page number
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- offset (address within page)
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page table indicates for each page which frame it's stored in.
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- paging allows a process to be stored noncontigously in memory.
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-it is a way of implementing run-time address binding
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## memoy protection valid/invalid bits
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each process takes up n pages. but the table typically has more than n entries.
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So the page table stores a valid/invalid bit which is set to invalid for out-of-range memory refs
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vald bits can also be changed to read only, read-write etc
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## fast memory (cache) for paging
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fastest is to store page table in special registers
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- not feasible if page table is large (which is usually is)
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- alternative is to store page table in main memory
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- can slow things down
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- because to access an address in memory, we now need two or more memory accesses
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- solution is to keep a cach eof table table entries that have been used recently, in a special set of paallel-access registers calles associateive registers
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- aka Translation look-aside buffer (TLB) |