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| title | aliases | tags | sr-due | sr-interval | sr-ease | ||
|---|---|---|---|---|---|---|---|
| 21-memory-management |
|
2022-11-22 | 14 | 250 |
storage heirachy
primary storage - cache and main memory
secondaryy - hard drive
as we move from secondary to primary:
- access speed increases
- access time decreases
- cost increases
- capacity decreases
process memory image and logical and physical addresses
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a program is compiled and linked into a process image before loading into memory for execution
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a process memory image consists of code section, data sections, lib sections, and stack sections
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each process has its own logical memory space starting from 0 and ending at a maximum address
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the logical address has to be translated into physical address before sending the memory request to the physical memory modules
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the memory management unit (MMU) translated between the logical addresse and the physical addresses.
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physical mode - progam refers directly to physical address
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protected mode - dont allow program to use physical address directly - uses logical address
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OS kernel creates a map from logical address to the physical address using a mapping table
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CPUrefers to this table to map between physical and logical address
paging for memory translation
Noncontiguous paging: a processes logica address pace is broken int fixed size units called pages, and main memory is broken into units of the same size, called frames.
in a paged memory allocation scheme, the logical sddresses generated by the CPU are broken by special ardware itno two components:
- page number
- offset (address within page)
page table indicates for each page which frame it's stored in.
- paging allows a process to be stored noncontigously in memory. -it is a way of implementing run-time address binding
memoy protection valid/invalid bits
each process takes up n pages. but the table typically has more than n entries. So the page table stores a valid/invalid bit which is set to invalid for out-of-range memory refs
vald bits can also be changed to read only, read-write etc
fast memory (cache) for paging
fastest is to store page table in special registers
- not feasible if page table is large (which is usually is)
- alternative is to store page table in main memory
- can slow things down
- because to access an address in memory, we now need two or more memory accesses
- solution is to keep a cach eof table table entries that have been used recently, in a special set of paallel-access registers calles associateive registers
- aka Translation look-aside buffer (TLB)