vault backup: 2022-07-19 21:01:12

content/notes/02-combinatorial-logic.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc204
 - lecture
-sr-due: 2022-07-19
-sr-interval: 3
+sr-due: 2022-07-27
+sr-interval: 8
 sr-ease: 250
 ---
 
@@ -13,7 +13,11 @@ sr-ease: 250
 
 
 
-
+- [transistors](notes/transistors.md)
+- [combinatorial-logic-circuit](notes/combinatorial-logic-circuit.md)
+- [boolean-equations](notes/boolean-equations.md)
+- [logic-gates](notes/logic-gates.md)
+- [demultiplexor](notes/demultiplexor.md)
 
 
 

content/notes/07-testing.md

@@ -4,8 +4,8 @@ tags:
 - cosc202 
 - lecture
 
-sr-due: 2022-06-9
-sr-interval: 22
+sr-due: 2022-11-09
+sr-interval: 113
 sr-ease: 270
 ---
 - [testing](notes/testing.md)

content/notes/boolean-equations.md

@@ -5,7 +5,7 @@ tags:
 - cosc204
 ---
 
-Often used to describe/define Combinatorial logic circuits
+Often used to describe/define [combinatorial-logic-circuit](notes/combinatorial-logic-circuit.md)
 
 # Precedence
 Precedence

content/notes/combinatorial-logic-circuit.md

@@ -14,10 +14,9 @@ They can be described using logic expressions and therefore logic gates. We assu
 
 They can be defined:
 - Using a truth table
-- Using boolean equations ($Q\ =\ A+\ B$) 
+- Using [boolean-equations](notes/boolean-equations.md) ($Q\ =\ A+\ B$) 
 - Using graphical symbols
 
-
 # Notable Examples
 - [1 Bit half adder](https://i.imgur.com/mjCVU4I.png)
 - [1 Bit full adder: (includes carry input)](https://i.imgur.com/yu6kS83.png)

content/notes/cosc-204.md

@@ -18,7 +18,10 @@ tags:
 - [digital-data](notes/digital-data.md)
 - [memory](notes/memory.md)
 - [boolean-equations](notes/boolean-equations.md)
-- 
+- [combinatorial-logic-circuit](notes/combinatorial-logic-circuit.md)
+- [logic-gates](notes/logic-gates.md)
+- [transistors](notes/transistors.md)
+- [demultiplexor](notes/demultiplexor.md)
 
 - Hardware
 - Assembly

content/notes/demultiplexor.md

@@ -0,0 +1,12 @@
+---
+title: "demultiplexor"
+aliases: 
+tags: 
+- cosc204
+---
+
+
+# Demultiplexor
+- Mutli way swtich where the address determines which output recieves the input
+
+![2 bit address diagram and truth table](https://i.imgur.com/XQteI3j.png)

content/notes/logic-gates.md

@@ -0,0 +1,15 @@
+---
+title: "logic-gates"
+aliases: 
+tags: 
+- cosc204
+---
+
+
+# Logic Gates
+- NOT
+- AND
+- OR
+- NAND
+- NOR
+- XOR/EOR

content/notes/transistors.md

@@ -0,0 +1,21 @@
+---
+title: "transistors"
+aliases: 
+tags: 
+- cosc204
+---
+
+
+# Transistors
+![simple transistor diagram|100](https://i.imgur.com/oBuNR9m.png)
+
+- B: Base ⇒ A swtich connecting C to E
+	- open (C is disconnected from E) when supplied 0v
+	- closed (C is connected to E) by applying +5V
+- C: Collector
+- E: Emitter
+
+Possible to create NAND gate using just transistors ∴ possible to create all logic gates using only transistors [^3]
+
+
+[^3] : They dont actually do it this way (see lab)