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content/notes/23-IO-systems.md
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@ -8,13 +8,12 @@ tags:
interactive between device drivers and IO devices interactive between device drivers and IO devices
# Hardware Hardware
- IO device linked to machine via Port - IO device linked to machine via Port
- link is a set of wires called a Bus - link is a set of wires called a Bus
- as each end of the link is a device controller (basically a process) - as each end of the link is a device controller (basically a process)
- ![diagram|400](https://i.imgur.com/qnmTxrb.png) - ![diagram|400](https://i.imgur.com/qnmTxrb.png)
- ![more complete diagram of PCI bus|400](https://i.imgur.com/fbJqpwr.png)
![more complete diagram of PCI bus|400](https://i.imgur.com/fbJqpwr.png)
device controller registers device controller registers
- each contoller has registers for holding signals - each contoller has registers for holding signals
@ -26,6 +25,32 @@ adressesing devices
- CPU can issue IO instructions to particular addresses - CPU can issue IO instructions to particular addresses
- communication can be 1 byte at a time for via direct memory access - communication can be 1 byte at a time for via direct memory access
# Kernel interface polling
- CPU cycles waiting for busy bit to be clear is known as polling (busy waiting)
- waste CPU time
- if CPU is polling for input from devices too, then all devices have to be monitored - this is big waste of CPU time
# Performance interupts
- used for communcation with IO devices: prefered over polling
- CPU hardware contains wire calld interrupt request line
- if cpu senses this line after each instruction it executes
- if intr sensed, CPU saves its current location and jumps to address in the interrupt vector indicated by the signal
- maskable/nonmaskable
- deal with different priorities of interrupt
- maskable: device generated, can be diabled when OS is processing a more urgent intr
- nonmaskable: for error messges, never disabled
Direct memory access
- sending large amounts of data to IO devices
- special purpose process DMA controller used
- CPU writes a DMA command block into memory, specifying which bytes to transfer, and where to put them
- DMA then controller can then execute concurrently
- after transfer is finsished DMA controller interrupts CPU
IO performance
- reduce context switches
- reduce data copies in memory (normamly two: user mem)
- reduce number of interrupts (e.g., using polling)
- increase concurrency (e.g., DMA)
- move data processing to hardware (e.g., network interface card)
- balance CPU, memory system, bus, IO performance