vault backup: 2022-11-01 12:04:33

content/notes/16-networks.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-20
-sr-interval: 3
+sr-due: 2022-11-24
+sr-interval: 23
 sr-ease: 250
 ---
 

content/notes/19-network-layer-data-plane.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-21
-sr-interval: 3
+sr-due: 2022-11-20
+sr-interval: 19
 sr-ease: 250
 ---
 

content/notes/20-network-layer-control-plane.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-21
-sr-interval: 3
+sr-due: 2022-11-23
+sr-interval: 22
 sr-ease: 250
 ---
 

content/notes/21-data-link-layer.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-21
-sr-interval: 3
+sr-due: 2022-11-22
+sr-interval: 21
 sr-ease: 250
 ---
 

content/notes/21-memory-management.md

@@ -4,6 +4,9 @@ aliases:
 tags: 
 - cosc204
 - lecture
+sr-due: 2022-11-04
+sr-interval: 3
+sr-ease: 250
 ---
 
 # storage heirachy
@@ -29,7 +32,7 @@ as we move from secondary to primary:
  - OS kernel creates a map from logical address to the physical address using a mapping table
  - CPUrefers to this table to map between physical and logical address
 
-![address bidning for process space slide|400](https://i.imgur.com/N0iAw0z.png)
+![address binding for process space slide|400](https://i.imgur.com/N0iAw0z.png)
 
 # paging for memory translation
 
@@ -39,4 +42,30 @@ in a paged memory allocation scheme, the logical sddresses generated by the CPU
 - page number
 - offset (address within page)
 
-![](https://i.imgur.com/i3dn9IP.png)
+![diagram|400](https://i.imgur.com/i3dn9IP.png)
+
+page table indicates for each page which frame it's stored in.
+
+- paging allows a process to be stored noncontigously in memory. 
+-it is a way of implementing run-time address binding
+
+![Example](https://i.imgur.com/L0TDBF0.png)
+
+## memoy protection valid/invalid bits
+each process takes up n pages. but the table typically has more than n entries.
+So the page table stores a valid/invalid bit which is set to invalid for out-of-range memory refs
+
+![diagam|400](https://i.imgur.com/gXLCCwg.png)
+
+vald bits can also be changed to read only, read-write etc
+
+![paging example](https://i.imgur.com/59hFyHd.png)
+
+## fast memory (cache) for paging
+fastest is to store page table in special registers
+- not feasible if page table is large (which is usually is)
+- alternative is to store page table in main memory
+	- can slow things down
+	- because to access an address in memory, we now need two or more memory accesses
+- solution is to keep a cach eof table table entries that have been used recently, in a special set of paallel-access registers calles associateive registers
+	- aka Translation look-aside buffer (TLB) 

content/notes/22-LAN-physical-layer.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-22
-sr-interval: 3
+sr-due: 2022-11-19
+sr-interval: 18
 sr-ease: 250
 ---
 

content/notes/23-wireless-mobile.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-23
-sr-interval: 3
+sr-due: 2022-11-19
+sr-interval: 18
 sr-ease: 250
 ---
 

content/notes/24-network-security.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-23
-sr-interval: 3
+sr-due: 2022-11-20
+sr-interval: 19
 sr-ease: 250
 ---
 

content/notes/25-advanced-topics.md

@@ -4,8 +4,8 @@ aliases:
 tags: 
 - cosc203
 - lecture
-sr-due: 2022-10-25
-sr-interval: 3
+sr-due: 2022-11-17
+sr-interval: 16
 sr-ease: 250
 ---