From 478f3ac3d07ab235a01b4f6fe5e336a2275f7745 Mon Sep 17 00:00:00 2001 From: Jet Hughes Date: Tue, 26 Jul 2022 14:38:15 +1200 Subject: [PATCH] vault backup: 2022-07-26 14:38:15 --- content/notes/combinatorial-logic-circuit.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/content/notes/combinatorial-logic-circuit.md b/content/notes/combinatorial-logic-circuit.md index 351a15d72..3326b33b4 100644 --- a/content/notes/combinatorial-logic-circuit.md +++ b/content/notes/combinatorial-logic-circuit.md @@ -18,13 +18,13 @@ They can be defined: - Using graphical symbols # Notable Examples -- [1 Bit half adder](https://i.imgur.com/mjCVU4I.png) -- [1 Bit full adder: (includes carry input)](https://i.imgur.com/yu6kS83.png) -- [Ripple carry adder](https://i.imgur.com/HtEIZ5t.png) +- ![1 Bit half adder](https://i.imgur.com/mjCVU4I.png) +- ![1 Bit full adder: (includes carry input)](https://i.imgur.com/yu6kS83.png) +- ![Ripple carry adder](https://i.imgur.com/HtEIZ5t.png) - 3 Bit parity Generator - Adds an extra bit to the input data so that the number of ones in the output is always odd - Used for error checking - [truth table](https://i.imgur.com/KDUiJbN.png) - [boolean equation](https://i.imgur.com/mwBpnlO.png) - [circuit](https://i.imgur.com/tsgDISC.png) -- [7 segment displlay](https://i.imgur.com/qtPmtwR.png) \ No newline at end of file +- ![7 segment displlay](https://i.imgur.com/qtPmtwR.png) \ No newline at end of file